To meet increasing performance demands in a compute environment there is a trend to increase the number of processing cores and memory bandwidth for processor components. Typically, as the number of processing cores and memory bandwidth increase so does the number of memory channels. However, different users may require different performance demands. Thus, a one size fits all approach is cost prohibitive and does not work. Current solutions statically configure memory channels and core counts based on price and performance. However, statically configuring limits original equipment manufacturers flexibility and can lead to divergent designs. Thus, embodiments discussed herein solve these and other problems to provide a more flexible approach for compute systems.